The three most critical points for a good PCB electromagnetic compatibility (EMC) design

Regarding the issue of EMC design in PCB, it should be a big problem for many Electronic hardware engineers. For example: How to consider EMC when PCB stacking? Are the same things that need to be considered when designing EMC for boards with different layers? Considering that everyone has questions about similar issues, the editor over there has compiled this article on how to do a good job of EMC design in PCB today, and I hope it will be helpful to you.

Regarding the issue of EMC design in PCB, it should be a big problem for many electronic hardware engineers. For example: How to consider EMC when PCB stacking? Are the same things that need to be considered when designing EMC for boards with different layers? Considering that everyone has questions about similar issues, the editor over there has compiled this article on how to do a good job of EMC design in PCB today, and I hope it will be helpful to you.

One, the layout of the device

In the process of PCB design, from the EMC perspective, three main factors must be considered first: the number of input/output pins, device density and power consumption.

A practical rule is that the area occupied by the chip components is 20% of the substrate, and the power dissipation per square inch is not more than 2W.

In terms of device layout, in principle, devices related to each other should be placed as close as possible, digital circuits, analog circuits, and power circuits should be placed separately, and high-frequency circuits should be separated from low-frequency circuits.

Devices that are prone to noise, low-current circuits, and high-current circuits should be kept away from logic circuits as much as possible. Main interference and radiation sources such as clock circuits and high-frequency circuits should be arranged separately, far away from sensitive circuits, and input and output chips should be located close to the I/O outlet of the hybrid circuit package.

High-frequency components should be connected as short as possible to reduce distribution parameters and mutual electromagnetic interference. Components that are susceptible to interference should not be too close to each other, and input and output should be kept as far away as possible. The oscillator is as close as possible to the location where the clock chip is used, and away from the signal interface and low-level signal chip.

The components should be parallel or perpendicular to one side of the substrate, and the components should be arranged in parallel as much as possible. This will not only reduce the distribution parameters between the components, but also conform to the manufacturing process of the hybrid circuit, which is easy to produce.

The lead-out pads for power and ground on the hybrid circuit substrate should be arranged symmetrically, and it is best to evenly distribute many power and ground I/O connections. The mounting area of ​​the bare chip is connected to the most negative potential plane.

When selecting a multilayer hybrid circuit, the layout of the circuit board varies with the specific circuit, but it generally has the following characteristics:

(1) The power supply and ground layer are distributed in the inner layer, which can be regarded as a shielding layer, which can well suppress the inherent common mode RF interference on the circuit board and reduce the distributed impedance of the high-frequency power supply.

(2) The power plane and the ground plane in the board are as close as possible to each other. Generally, the ground plane is above the power plane. In this way, the interlayer capacitance can be used as a smoothing capacitor for the power supply. At the same time, the ground plane shields the radiation current distributed by the power plane.

(3) The wiring layer should be arranged as close as possible to the power or ground plane to produce flux cancellation.

Two, PCB routing

In circuit design, often only focus on increasing the wiring density, or the pursuit of uniform layout, ignoring the influence of the wiring layout on the prevention of interference, causing a large number of signals to radiate into the space to form interference, which may cause more electromagnetic compatibility problems.

Therefore, good wiring is the key to the success of the design.

1. The layout of the ground wire

The ground wire is not only a potential reference point for circuit work, but also a low-impedance loop for signals.

The most common interference on the ground wire is the ground loop interference caused by the ground loop current. Solving this type of interference problem is equivalent to solving most of the electromagnetic compatibility problems.

The noise on the ground wire mainly affects the ground level of the digital circuit, and when the digital circuit outputs a low level, it is more sensitive to the noise on the ground wire.

The interference on the ground wire may not only cause the malfunction of the circuit, but also cause conduction and radiation emission. Therefore, the key to reducing these interferences is to reduce the impedance of the ground wire as much as possible (for digital circuits, reducing the ground wire inductance is particularly important).

Pay attention to the following points in the layout of the ground wire:

(1) According to different power supply voltages, the digital circuit and the analog circuit are separately set to ground.

(2) The common ground wire should be as thick as possible. When using a multi-layer thick film process, the ground plane can be specially set, which helps to reduce the loop area and also reduces the efficiency of the receiving antenna. And can be used as a shield for signal lines.

(3) Comb ground wires should be avoided. This structure makes the signal return loop large, which will increase radiation and sensitivity, and the common impedance between chips may also cause misoperation of the circuit.

(4) When multiple chips are installed on the board, a large potential difference will appear on the ground wire. The ground wire should be designed as a closed loop to improve the noise tolerance of the circuit.

(5) For circuit boards with both analog and digital functions, the analog ground and digital ground are usually separated and only connected at the power source.

2. Layout of the power supply circuit

Generally speaking, in addition to interference directly caused by electromagnetic radiation, electromagnetic interference caused by power lines is the most common. Therefore, the layout of the power cord is also very important. Generally, the following rules should be observed.

(Power handling)

(1) The power line is as close as possible to the ground line to reduce the area of ​​the power supply loop, and the differential mode radiation is small, which helps to reduce the circuit crosstalk. Do not overlap the power supply loops of different power supplies.

(2) When using multi-layer technology, the analog power supply and the digital power supply are separated to avoid mutual interference. Do not overlap the digital power supply with the analog power supply, otherwise coupling capacitors will be generated and the degree of separation will be destroyed.

(3) The power plane and the ground plane can be isolated by a complete dielectric. When the frequency and speed are high, a dielectric slurry with a low dielectric constant should be used. The power plane should be close to the ground plane and arranged below the ground plane to shield the radiation current distributed on the power plane.

(4) Decoupling should be carried out between the power supply pin and the ground pin of the chip. The decoupling capacitor adopts a 0.01uF chip capacitor, which should be installed close to the chip to minimize the loop area of ​​the decoupling capacitor.

(5) When selecting a SMD chip, try to choose a chip with the power pin and the ground pin close to each other, which can further reduce the area of ​​the power supply loop of the decoupling capacitor, which is conducive to achieving electromagnetic compatibility.

3. Processing of signal lines

When using a single-layer thin film process, a simple and applicable method is to first lay out the ground wire, then place key signals, such as high-speed clock signals or sensitive circuits, close to their ground loops, and finally route other circuits.

The layout of the signal lines is best arranged according to the order of the signal flow, so that the signal on the circuit board flows smoothly.

If you want to minimize EMI, make the signal line as close as possible to the return signal line formed with it, and make the loop area as small as possible to avoid radiation interference.

Low-level signal channels should not be close to high-level signal channels and unfiltered power lines, and wiring sensitive to noise should not be parallel to high-current, high-speed switching lines. If possible, arrange all key traces as strip lines. Incompatible signal lines (digital and analog, high-speed and low-speed, high-current and low-current, high-voltage and low-voltage, etc.) should be kept away from each other and should not be routed in parallel.

The crosstalk between signals is extremely sensitive to the length of adjacent parallel traces and the trace spacing, so try to increase the distance between high-speed signal lines and other parallel signal lines and reduce the parallel length.

The inductance of the conduction band is proportional to its length and the logarithm of the length, and inversely proportional to the logarithm of its width.

Therefore, the conduction band should be as short as possible, and the address lines or data lines of the same component should be as consistent in length as possible. The wires used as the input and output of the circuit should be avoided as far as possible. . The wiring density of low-speed signals can be relatively large, and the wiring density of high-speed signals should be as small as possible.

(Try to stagger the parallel lines of adjacent layers)

In the multi-layer thick film process, in addition to complying with the rules of single-layer wiring, you should also pay attention to:

Try to design a separate ground plane, and the signal layer is arranged adjacent to the ground layer. When it cannot be used, a ground wire must be set near the high-frequency or sensitive circuit.

The signal lines distributed on different layers should be perpendicular to each other, so as to reduce the electric field and magnetic field coupling interference between the lines; the signal lines on the same layer should be kept at a certain distance, and it is best to isolate them with corresponding ground loops to reduce signal crosstalk between lines.

Each high-speed signal line should be restricted to the same layer. The signal line should not be too close to the edge of the substrate, otherwise it will cause the characteristic impedance to change, and it is easy to produce fringe fields and increase the outward radiation.

4. Clock circuit processing

The clock circuit occupies an important position in the digital circuit, and at the same time is the main source of electromagnetic radiation.

The radiated energy spectrum of a clock signal with a rising edge of 2ns can reach 160MHz. Therefore, designing a good clock circuit is the key to ensuring the electromagnetic compatibility of the entire circuit.

(Clock circuit)

Regarding the layout of the clock circuit, there are the following precautions:

(1) Do not use a daisy chain structure to transmit clock signals, but a star structure, that is, all clock loads are directly connected to the clock power driver.

(2) The conduction bands connected to the input/output terminals of the crystal oscillator should be as short as possible to reduce noise interference and the influence of distributed capacitance on the crystal oscillator.

(3) The crystal capacitor ground wire should be connected to the device with the widest and shortest possible conduction band; the digital ground pin closest to the crystal should minimize vias.

Third, the selection of process and components

There are three manufacturing processes for hybrid integrated circuits to choose from, single-layer thin film, multi-layer thick film and multi-layer co-fired thick film.

Thin film technology can produce small size, low power and high current density components required by high-density hybrid circuits. It has the characteristics of high quality, stability, reliability and flexibility. It is suitable for high-speed, high-frequency and high-packing density circuits. Only single-layer wiring can be done and the cost is relatively high.

The multi-layer thick film process can manufacture multi-layer interconnection circuits at a lower cost. From the perspective of electromagnetic compatibility, multi-layer wiring can reduce the electromagnetic radiation of the circuit board and improve the anti-interference ability of the circuit board.

Because you can set up a dedicated power layer and ground layer, the distance between the signal and the ground wire is only the inter-layer distance. In this way, the loop area of ​​all signals on the board can be minimized, thereby effectively reducing differential mode radiation.

Among them, the multi-layer co-fired thick film process has more advantages and is currently the mainstream technology of passive integration. It can achieve more layers of wiring, easy to embed components, improve assembly density, and have good high-frequency characteristics and high-speed transmission characteristics.

In addition, it has good compatibility with thin film technology, and the combination of the two can achieve hybrid multilayer circuits with higher assembly density and better performance.

Active devices in hybrid circuits generally use bare chips. When there are no bare chips, you can use the corresponding packaged chips. In order to get the best EMC characteristics, try to use surface-mount chips.

When choosing a chip, try to choose a low-speed clock under the premise of meeting the product’s technical indicators. Never use AC when HC can be used, and CMOS4000 can do without HC. The capacitor should have a low equivalent series resistance, so as to avoid large attenuation to the signal.

The encapsulation of the hybrid circuit can adopt Kovar metal base and cover, parallel seam welding, which has a good shielding effect.

In order to help you design the electromagnetic compatibility (EMC) circuit of electronic and electrical products, and solve the problem of circuit signal radiation caused by electromagnetic interference emission and signal conduction emission, the editor has selected a super dry electromagnetic compatibility EMC study for everyone. The data spree includes 70+ EMC classic circuit data, 100 minutes to teach you EMC case analysis and simulation video tutorials.

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Author: Yoyokuo