The ADRV9040 offers eight transmit and receive channels of 400MHz bandwidth and integrates advanced DSP functions, including carrier digital up-converters (CDUC), carrier digital down-converters (CDDC), crest factor reduction (CFR) and digital pre-distortion (DPD).
These capabilities can eliminate the need for an FPGA, thereby reducing thermal footprint, and total system size, weight, power, and cost.
The chip’s DPD algorithms were developed using ML techniques and are optimised in close collaboration with major PA vendors to ease the design burden and deliver wide bandwidth performance.
The algorithms are fully tested and validated across 4G and 5G use cases, including various PA technology types such as GaN.
In addition, the ZiF radio architecture simplifies RF filtering and signal chain components, reducing RU cost and development time for band and power variants designs.
Learn more about the ADRV9040 RadioVerse SoC at http://www.analog.com/ADRV9040