“In the high-speed data acquisition system, if the A/D converter is directly connected to the microprocessor MCU, the high-speed A/D conversion rate will force the MCU to continuously read the conversion results, thus occupying most of the MCU The high I/O bandwidth reduces the working efficiency of the MCU. In this case, a buffer is usually added, so that “A/D converter buffer-processor” becomes a universal mode. Here’s how to use the FIFO chip CY7C4255V to realize the interface between the high-speed and high-precision analog/digital converter AD767l and the LPC2200 series of ARM processors.
In the high-speed data acquisition system, if the A/D converter is directly connected to the microprocessor MCU, the high-speed A/D conversion rate will force the MCU to continuously read the conversion results, thus occupying most of the MCU The high I/O bandwidth reduces the working efficiency of the MCU. In this case, a buffer is usually added, so that “A/D converter buffer-processor” becomes a universal mode. Here’s how to use the FIFO chip CY7C4255V to realize the interface between the high-speed and high-precision analog/digital converter AD767l and the LPC2200 series of ARM processors.
1. Introduction to the device
1.1 Analog/digital converter AD7671
AD767l is a 16-bit successive approximation high-speed and high-precision analog-to-digital converter with a sampling rate of 1Msps. It adopts a 5V single power supply and can provide unipolar and bipolar input modes, which can be applied to different input ranges; it It also provides calibration and error correction circuit, internal clock, 8-bit or 16-bit parallel port and 1 serial port. AD7671 can reach 16-bit resolution without missing codes, and the maximum integral nonlinear error (INL) is only 2.5 LSB, which can meet the requirements of various high-precision applications.
Under normal circumstances, AD7671 has two data reading methods: one is to read the converted data after the data conversion is completed; the other is to read the last converted data during the data conversion process. The timing diagram in Figure 1 describes the latter case, that is, the main controller detects the BUSY signal after sending the CNVST signal. When the BUSY signal is set to high level, the data converted by the previous conversion process is read.
1.2 FIFO chip CY7C4255V
FIFO (First In First Out) simply means first in first out. As a new type of large-scale integrated circuit, FIFO chips are gradually being used more and more widely in high-speed data acquisition, high-speed data processing, high-speed data transmission, and multi-computer processing systems with their flexible, convenient, and efficient characteristics. CY7C455V is Cypress’s 3.3V high-speed, low-power FIFO, the chip capacity is 8K18 bits, the highest operating rate is 100MHz (the shortest read/write time is 10ns), and the input/output ports are controlled by separate clocks and enable signals , With “empty”, “full”, “half full” and programmable “almost empty” and “almost full” signs.
The 18-bit input/output port of CY7C4255 is controlled by a separate clock and enable signal. The input port is controlled by a continuous write clock (WCLK) and write enable signal (WEN). When the write enable WEN is valid, data is continuously written into the FIFO memory on the rising edge of the WCLK signal in each clock cycle. Similarly, the output port is controlled by a continuous read clock (RCLK) and read enable signal (REN), and there is an output enable pin (OE). If it is a single clock operation, the read/write clocks can be connected together; in asynchronous read/write applications, the two clocks can be independent, and the clock frequency can be up to 100 MHz. The cascade input (WXI, RXI), cascade output (WXO, RXO) and first load (FL) pins provided by the chip can be used for deep expansion.
1.3 ARM processor LPC2210
LPC2210 is a microcontroller based on a 16/32-bit 144-pin ARM7TDMI-S core that supports real-time simulation and embedded tracking. It contains internal ARM7TDMI-S core and the on-chip memory controller interface ARM7 local bus, AMBA high-performance bus (AHB) interface with the interrupt controller and VLSI peripheral bus (VPBARM AMBA bus compatible with the on-chip peripheral functions) set). LPC2210 has 16KB on-chip static RAM; the connection between on-chip peripherals and device pins is controlled by the pin connection module, which is controlled by software to meet the requirements of peripheral functions and pins in specific applications; through the external memory interface Configure the memory into 4 groups, the capacity of each group is up to 16MB, and the data width is 8/16/32 bits; with 2 32-bit timers (with 4 capture and 4 comparison channels), PWM unit (6 outputs) , Real-time clock and watchdog; multiple serial interfaces including 2 16C550 industrial standard UART, high-speed I2C interface (400kb/s) and 2 SPI interfaces; up to 76 general I/O ports (withstand 5V voltage) , 12 independent external interrupt pins EIN and CAP function.
2. Interface circuit
Utilize FIFO chip CY7C4255V to realize the interface circuit of AD7671 and LPC2210, as shown in Fig. 2. In the figure, the input range of AD7671 has been configured to ±5V, and its data port adopts a high-speed parallel interface; the data reading mode of the interface is set to the mode shown in Figure 1, where +5V and -5V are analog voltages respectively. Because the voltage of the data interface of CY7C11255V and LPC2210 is 3.3V, input 3.3V digital voltage to OVDD pin, so the data interface voltage of AD7671 can be compatible with the data interface of FIFO chip. ADR421 provides +2.5V reference voltage for AD7671; AD7671’s analog input end uses a drive circuit composed of low noise figure driver amplifier ADS02l to drive A137671.
The A/D conversion result output is directly connected with the FIFO data input terminals D0～D15} Conversion control A PWM output terminal of the ARM processor generates a sampling control signal of the required sampling frequency, which is also used as the control of the input enable terminal of the FIFO . The BUSY output terminal of AD767l is used as the FIFO input clock (WCLK) control signal. When the conversion ends, BUSY (WCLK) changes from low to high. At this time, the FIFO write enable WEN is valid, and the conversion data is on the rising edge of the WCLK (BUSY) signal. It is written into the FIFO memory. The LPC2210 ARM processor bus data width is configured as 16 bits, and the FIFO data reading is controlled by the EMC bus chip selection signal nCS2, output enable signal nOE, and clock output XCLK. The half full (HF) and full full (FF) flags of FIFO are connected to the two interrupt pins of ARM, which can be selected for use in practical applications through programming; EF is connected to PO of ARM. Pin 23 is used as the empty query pin of the FIFO.
FIFO device is used as the data buffer between the high-speed A/D and ARM processor, which has the advantages of simple circuit structure and reliable performance; at the same time, it improves the working efficiency of the processor and makes the control more convenient.