In high-performance motors and servo drives, isolated sigma-delta (Σ-Δ) based analog-to-digital converters (ADCs) have become the preferred method for measuring phase currents. These converters are known for their strong galvanic isolation and excellent measurement performance. With the introduction of new generations of ADCs, their performance is constantly improving, but to take full advantage of the latest ADC’s capabilities, other motor drivers need to be designed accordingly.

**Introduction**

Motor drive manufacturers continue to improve the performance and robustness of their products. Some of the improvements are achieved by employing more advanced control algorithms and higher computing power. Other improvements are achieved by minimizing non-ideal effects in the feedback circuit, such as delay, tilt, and temperature drift.

As far as feedback to the motor control algorithm is concerned, the most critical part is the measurement of the phase currents. As control performance improves, systems become more sensitive to nonideal effects such as timing accuracy, offset/gain errors, synchronization of multiple feedback channels, etc. semiconductor companies have worked to reduce these nonideal effects in the feedback signal chain for years, and this trend is likely to continue. The ADuM7701 is an example of the latest generation of isolated Σ-Δ ADCs optimized for measuring phase currents. While the performance of the ADC is important, it is also likely to cause non-ideal effects in the rest of the feedback path. This article does not consider ADCs and focuses on the rest of the feedback path. While this article focuses on motor control applications, it is also applicable to any other system that requires tight synchronization of sigma-delta ADCs.

A typical signal chain when using a sigma-delta ADC is shown in Figure 1. The analog input voltage is generated by passing the phase currents through a resistive shunt. The sigma-delta ADC converts the analog signal into a 1-bit data stream and provides electrical isolation, so everything after the ADC is galvanically isolated from the motor phases. The converter is followed by demodulation performed by filtering. This filter converts a 1-bit signal to a multi-bit (M-bit) signal and reduces the data update rate through a decimation process. While filter decimation reduces the data rate, the rate is often still too high to match the update rate of the control algorithm. To address this issue, we add a final downsampling stage.

This article assumes that the filter and decimation stages are implemented in an FPGA, and that the filter is a third-order sinc filter (sinc3).

Figure 1. A sigma-signal chain for measuring phase current.

Figure 2. (a) Sinc filter impulse response with a filter decimation rate of 5. (b) The step response of the Sinc filter and its relationship to the impulse response.

Sinc filter synchronization

The disadvantage of sigma-delta ADCs and sinc filters is that they are difficult to control in the same time domain and lack a specified sampling instant. 2 Both filters have some concerns compared to traditional ADCs with dedicated sample-and-hold circuits. However, there are ways to solve this problem. As shown in this section, it is critical to synchronize the sinc filter with the rest of the system and sample the phase currents at the appropriate moments. If this is not done correctly, the measurement results will be greatly distorted.

The output of the sinc filter does not represent the input of the sigma-delta ADC at that moment. Instead, the output is a weighted average of the inputs during past windows. This is due to the impulse response of the filter. Figure 2a shows the impulse response of sinc3 at a decimation rate of 5. You can see from the figure how the filter output becomes a weighted sum of the input sequence, with samples in the middle getting a larger weight and samples at the beginning/end of the sequence getting a lower weight.

Before continuing the discussion, a few basic definitions need to be given. The sigma-delta ADC clock, also known as the modulator clock, is denoted fmod. The decimation ratio (DR) determines the decimation frequency (fdec) and is related to fmod as shown in Equation 1:

The right side of Figure 2 shows the effect of the impulse response on the filter’s step response. When this step is applied, the filter output is unaffected and the filter reaches steady state after 3 complete decimation cycles. Therefore, some important properties of the sinc3 filter can be expressed as:

Group delay of 1.5 decimation cycles

Settling time is 3 decimation cycles

These properties are very important when synchronizing the filter with the control system and will be used throughout this article.

Before discussing sinc filter synchronization, the characteristics of the input signal must be defined. This in turn defines the synchronization characteristics of the filter.

Figure 3 shows the simulated phase currents of a 3-phase permanent magnet motor driven by a voltage source inverter. The modulation method is space vector PWM3, and the switching frequency is 10 kHz. Load the motor to 5 A peak phase current and 3000 rpm speed. This setup plus 3 pole pairs gives an electrical fundamental period of 6.67 ms.

Figure 3. Motor phase currents with space vector pulse width modulation.

The phase current can be seen as consisting of two components: the average component and the switching component. For control purposes, only the average component of the current is of interest, so the switching component must be completely removed. To extract the average component, the most common method is to sample a signal (for motor terminals) that is synchronized to the PWM. As shown in Figure 4. The top signal shows the switching waveform of the phase current, the middle signal shows the high-side PWM of the corresponding inverter phase arm, and the bottom signal shows the synchronization signal from the PWM timer. The PWM sync signal is asserted at the beginning and middle of the PWM cycle. For simplicity, it is assumed that the duty cycle of all three phases is 50%, which means that the current has only one rising and one falling ramp. On the rising edge of the PWM sync signal, the current takes its average value, so if the current is sampled at exactly that moment, the switching component will be completely suppressed. In effect, the sample-and-hold circuit acts as a filter with infinite attenuation at the switching frequency.

Figure 4. Measuring phase current at the start and center of the PWM cycle reduces current ripple.

Figure 5 shows the result when such sampling is applied to the waveform shown in Figure 3. Shown on the right is an enlarged view of the actual phase current and sampled current waveforms. Notice how the sample-and-hold process completely removes the ripple.

The sampled current is expressed per unit, where 0 A is mapped to 0.5, and the full scale value is 8 A. This scale was chosen for easier comparison with subsequent sigma-measurements. The result shown in Figure 5 is an ideal scenario where only the fundamental component remains after sampling. Therefore, these data can be used as reference values for comparing sigma-measured values.

Sigma-Measurement and Aliasing

In an ideal sample-and-hold ADC, since the sampling timing is strictly controlled, the fundamental component can be extracted. However, sigma-delta conversion is a continuous sampling process, and the ripple component will inevitably become part of the measurement.

In sigma-delta conversion, there is a close relationship between decimation rate and signal-to-noise ratio (SNR). The higher the decimation rate, the more effective bits (ENOB) of the output. The downside is that as the decimation rate increases, so does the group delay, so the designer must trade off between signal resolution and feedback chain delay. In general, the delay should be kept small compared to the control period. For motor control, a typical decimation rate is between 128 and 256, which provides a good balance between signal-to-noise ratio and group delay.

In the data sheet specification, 256 is usually used as the decimation rate. For example, the ENOB of the ADuM7701 is 14 bits with a decimation rate of 256. With such high ENOB values, very accurate measurements are expected. To verify this, assume that the phase currents shown in Figure 3 are measured at 20 MHz with a sigma-delta ADC and the data stream is demodulated by a sinc3 with a decimation rate of 256. The results are shown in Figure 6a.

Figure 5. Ideal phase current sampling: (a) fundamental period of ideal sampled phase current, (b) waveform magnification of phase current and sampled phase current.

Figure 6. (a) Output of the sinc filter. (B) The actual phase current and the sinc filter decimated output waveform enlargement.

Figure 7. (a) Sampled output of a sinc filter. (b) Measurement error.

The fundamental components of the phase currents are quite evident, but the measured signals are quite noisy compared to the ideal sampling shown in Figure 5a. So while the ADC and sinc filter themselves provide a decent number of ENOBs, the quality of the feedback signal is poor. The reason for this can be seen in Figure 6b, which is an enlarged view of the sinc filter output and the actual phase current waveforms. Notice how the 10 kHz switching component of the phase current is phase shifted and barely attenuated by the sinc filter. Now, suppose the motor control algorithm is executed every PWM cycle and the latest sinc filter output is read at the beginning of the cycle. In effect, the output of the sinc filter is downsampled to match the update rate of the control algorithm. The downsampled and resulting signal is shown as the sampled sinc output in Figure 6b. Figure 7a shows the result of filtering and sampling the entire fundamental cycle at the PWM rate.

It is clear that the phase current measurement is severely distorted and therefore the control performance will be very poor. As such, torque ripple should be increased and the bandwidth of the current control loop needs to be reduced. Subtracting the measurement in Figure 7a from the ideal measurement (Figure 5a) gives the error (Figure 7b). The error is about 7% of the original scaled signal, which is far from the expected 14 ENOB.

This sigma-delta measurement and aliasing scenario demonstrates a very common current measurement pattern based on sigma-delta and how it leads the designer to the conclusion that “sigma-delta ADCs are not suitable for motor drives”. However, this example does not show the poor performance of the ADC itself. Conversely, the remaining signal chain performed poorly because the phase current measurements were not set correctly.

The ADC samples the input signal at several megahertz (typically 10 MHz to 20 MHz), and at a decimation rate of 256, the sinc filter effectively removes modulation noise. At such high sampling rates, there is a phase current ripple component in the filter output, which can become a problem at the downsampling stage of the signal chain (see Figure 1). If the ripple component is not sufficiently attenuated and the motor control algorithm consumes current feedback at PWM speed, the results will alias due to downsampling.

According to standard sampling theory, to avoid aliasing, the signal must have no energy above half the sampling frequency. If the sigma-delta ADC output is downsampled to 10 kHz, noise at 5 kHz or higher will alias into the measurement. As shown, after the sinc filter, there is also a lot of 10 kHz switching noise in the signal. One way to reduce 10 kHz noise is to increase the decimation rate, but doing so results in an unacceptably long group delay. We need to take a different approach.

Improve measurements with synchronization

The main issues with the anti-aliasing approach discussed in the previous section are shown in Figure 8. The output of the sinc filter is read at a time independent of the phase current switching components. As the output signal is read, the filter performs a weighted average of the input signal based on the impulse response. This weighted average sometimes spans the lows and sometimes the highs of the switching waveform. Therefore, the signal used as feedback contains significant noise from 0 Hz to half the PWM frequency.

Figure 8. The impulse response is independent of the switching waveform.

The sigma-delta ADC samples continuously, and the sinc filter output is multiplied by the measurement per PWM cycle (typically 10 to 20). Since each measurement spans 3 decimation periods, the impulse responses overlap. For simplicity, only three measurements/impulse responses are shown in Figure 8.

Figure 9. (a) Sampled output of a sinc filter with PWM for impulse response locking. (b) Measurement error.

The root of the problem is that the impulse response is not locked to the switching component of the current, which in turn is locked to PWM. The solution is to choose the decimation rate so that each PWM cycle has a fixed integer decimation period. For example, if the PWM frequency is 10 kHz, the modulator clock is 20 MHz, and the decimation rate is 200, then there are exactly 10 decimation periods per PWM period. Each PWM cycle has a fixed sampling period, the impulse response is always locked to PWM, and the measurement used for feedback is captured at the same point in the PWM cycle. Phase current measurements with this synchronization scheme are shown in Figure 9a.

Obviously, synchronizing the response with the PWM has a positive effect. Noise is removed, and at first glance the measurement appears to be similar to the ideal measurement in Figure 5a. However, when the Σ-? measurement is subtracted from the ideal measurement, the error signal shown in Figure 9b is obtained. The magnitude of the error is similar to the value shown in Figure 7b, but the spectrum has changed. Now, the error is the first harmonic, which is equivalent to the gain error. The reason for this error mode is shown in Figure 10.

Figure 10. The impulse response is locked to a fixed point within the switching cycle.

Although the white noise error component is eliminated, the signal is still distorted because the measurement is affected by the switching component. In Figure 10, notice how the impulse response of the sinc filter gives a weighted average around the peaks of the switching waveform. Depending on the phase of the impulse response relative to the PWM, the magnitude of the deviation is limited only by the magnitude of the ripple current. As shown in Figure 3, the amplitude of the ripple component changes during the fundamental wave period, and the ripple is the highest at the peak value of the fundamental wave current and the lowest at the zero-crossing point. Therefore, the measurement error is a first-order harmonic component.

To eliminate first-order harmonic measurement errors, the impulse response must always be centered at the start or center of the PWM cycle, where the phase currents are exactly equal to their average values. Figure 11 shows the impulse response centered at the start of the switching cycle. Around this point, the switching waveform is symmetrical, so by having the same number of measurement points on each side, the ripple component is zero around this point.

Figure 11. The impulse response is locked to the switching period and aligned to the ideal measurement point.

When the impulse response is locked and centered on the moment of the average current, the measurement results are shown in Figure 12a, and the measurement error is shown in Figure 12b. As an ideal sampling measurement, this signal is free of white noise and gain errors.

It turns out that the quality of the Σ-? measurements depends not only on the decimation rate. The popular belief that “increasing the decimation rate increases ENOB” is true only when there is no aliasing. Controlling the update rate and phase of the filter relative to the input signal is more important than the decimation rate. For example, compare Figure 7 (based on a decimation rate of 256) and Figure 12 (based on a decimation rate of 200). Reducing the decimation rate can significantly improve the measurement results.

Figure 12. (a) The sampled output of the sinc filter when the impulse response is locked using PWM and centered on the average current moment. (b) Measurement error.

**in conclusion**

To sum up, the conditions for realizing the optimal phase current measurement value based on Σ-? are as follows:

The impulse response time of a third-order sinc filter is 3 decimation cycles, which means that it takes 3 decimation cycles for the data to pass through the filter.

The impulse response of the filter must be centered on the average current moment.

1.5 sample periods of the impulse response must precede the average current moment, and another 1.5 sample periods must follow the average current moment.

A sinc filter produces multiple outputs during a PWM cycle, but only uses one of them. The rest of the output is ignored.

**refer to**

1Jens Sorensen, Dara O’Sullivan: “A Systematic Approach to Understanding the Impact of Nonideal Effects in Motor Drive Current Loops.” Proceedings of PCIM, Europe, 2016.

2Jens Sorensen: “Sigma-Delta Conversion for Motor Control.” Proceedings of PCIM, Europe, 2015.

3Ahmet M. Hava, Russel J. Kerkman, Thomas A. Lipo: “A Simple Analytical and Graphical Approach for Carrier-Based PWM-VSI Drives.” IEEE Transactions on Power Electronics, January 1999.