Main control chip CPU/FPGA storage and single event flip science

semiconductor memory is a semiconductor device that can store a large amount of binary information. There are many types of semiconductor memory. Generally, they can be divided into read-only memory (ROM) and random access memory (RAM) according to their functions.

foreword

Every time the Shenzhou manned spacecraft and SpaceX satellites are launched, they can attract many people’s attention. For these mysterious spaceflights, do you know how their information is processed? The processing of spacecraft information relies on the CPU/FPGA, and the execution of instructions relies on memory. At present, most of the manufacturers selling main chips on the market started with memory. Here, Wolfe Yu, engineer of Excelpoint Shijian Company, introduced the classification of storage and their respective advantages and disadvantages.

Functional classification of semiconductor memory

Semiconductor memory is a semiconductor device that can store a large amount of binary information. There are many types of semiconductor memory. Generally, they can be divided into read-only memory (ROM) and random access memory (RAM) according to their functions.

The ROM structure is simple, and the data is retained after the power is turned off; when the power is turned on again, the read data can be restored to the original state.

Main control chip CPU/FPGA storage and single event flip science
Figure 1 ROM power-on information retention

RAM is different. After each power-on, the last information cannot be retained.

Main control chip CPU/FPGA storage and single event flip science
Figure 2 RAM re-power-on information lost

Read Only Memory (ROM)

Read-only memory is mainly divided into mask memory, programmable memory (PROM), electrically erasable programmable memory (EEPROM) and Flash and so on.

Early Read-Only Memory at a Glance

Mask read-only memory: customized products, according to user requirements, the internal data is set at the factory and cannot be modified later.

Programmable read-only memory: also called “anti-fuse”, it is more advanced than mask memory. It can be programmed once when it leaves the factory, but if it is burned wrongly, it has to be discarded and replaced with the next one.

EEPROM (E2PROM): In order to reuse, this generation of products first studied the first generation of EPROM products erased by ultraviolet light. This generation of products injects charge through a floating gate avalanche injection MOS tube (FAMOS), or a stacked gate avalanche injection MOS tube (SIMOS), and programs through the avalanche effect. This product is complicated to erase, and the erasing speed is very slow.

Later, after improvement and upgrade, the floating gate tunnel oxide MOS tube was used for injection, which was named “EEPROM”, also known as “E2PROM”. In order to improve the reliability of erasing and writing, and protect the tunnel oxide layer, the EEPROM will also add a strobe. When the program is read and written, the operation is mainly realized by applying pulses to the word lines and bit lines.

Main control chip CPU/FPGA storage and single event flip science
Figure 3 List of mask memory, antifuse memory, and EEPROM

Flash Memory

Flash memory Flash has made some improvements on the basis of EPROM and EEPROM. It uses a single-tube stacked-gate structure memory cell similar to EPROM, and only uses a single tube to achieve.

Main control chip CPU/FPGA storage and single event flip science
Figure 4 Flash memory cell structure

The structure of the flash memory Flash is similar to the SIMOS tube of EPROM. The main difference is that the thickness of the floating gate and the substrate oxide layer are different. The following figure is a stacked gate MOS tube structure of Flash.

Main control chip CPU/FPGA storage and single event flip science
Figure 5 Stacked gate MOS transistor structure of ordinary Flash

How exactly does flash memory store data? Flash erasing is achieved by changing the charge on the floating gate. When writing, the drain is connected to a positive voltage through the bit line, and the substrate is grounded. A pulsed high voltage (18~20V) is applied to the word line, and avalanche breakdown will occur between the source and drain, and some electrons will pass through. The oxide layer reaches the floating gate, forming a floating gate charge.

Erasing is accomplished by removing electrons from the floating gate. When erasing, ground the word line and at the same time, bias a positive pulsed high voltage (about 20V) on the P-well and N-substrate. At this time, the charge on the floating gate will be removed again through the tunnel effect.

When reading Flash, the normal logic level (generally 3.3V or 5V) is generally applied to the word line, and the source level is grounded. When there is charge on the floating gate, the MOS tube is turned off and a 1-state signal is output. On the contrary, there is no charge on the floating gate, the MOS transistor is turned on, and a 0-state signal is output.

Main control chip CPU/FPGA storage and single event flip science
Figure 6 Flash unit erasing example

Flash Over Erase

The essence of flash memory is a storage array, which is judged by comparing the charge on the floating gate with the logic level of the word line. Take Nor Flash as an example. According to the normal working method, when the word line works, normal logic (3.3V or 5V) will be added; if the word line does not work, it is usually left floating or input 0V level.

Under normal circumstances, when the word line is not working, no normal logic (3.3V or 5V) is applied to the gate, and the MOS tube is required to be turned off regardless of whether there is charge on the floating gate.

If the Flash is over-erased, at this time, the floating gate will appear as a high voltage, and the output voltage value is uncertain. If the voltage value can just make the MOS tube of the cell turn on, at this time, no matter which word line is selected, the read value of the bit line is 0V, which affects the reading and writing of other cells, which is called “cell leakage”. Therefore, in order to prevent Flash from being over-erased, care must be taken when erasing, so that the erasing time becomes longer.

Main control chip CPU/FPGA storage and single event flip science
Figure 7 Schematic diagram of Nor Flash operation

super flash memory®)

As mentioned earlier, flash memory is very powerful, but the erasing speed is too slow. In response to this problem, Wolfe Yu introduced a new super flash storage SuperFlash invented by SST, a subsidiary of Microchip, which is represented by Shijian.®technology.

Main control chip CPU/FPGA storage and single event flip science
Figure 8 SuperFlash®Stacked gate MOS transistor structure of flash memory

In SuperFlash flash memory, the control gate is divided into two parts, covering only part of the floating gate, which can directly control the current flowing into the drain.

The positive charge left behind by over-erase can create cell leakage paths that prevent the flash from reading data properly. For SuperFlash flash, since the control gate directly manages the drain edge, over-erase cannot make the leakage path of the floating gate reach the drain. Therefore, SuperFlash flash memory does not consider the problem of over-erasing, and relatively speaking, the erasing time will be much shorter.

Random Access Memory (RAM)

Random access memory, can read and write data anytime, anywhere, easy to read and write, flexible operation. However, RAM has the disadvantage of data volatility. RAM is mainly divided into two categories: dynamic random access memory (DRAM) and static memory (SRAM).

Dynamic Random Access Memory (DRAM) at a Glance

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a kind of semiconductor memory, the main function principle is to use the electric charge stored in the capacitor to represent a binary bit (bit). In reality, there is a leakage current in transistors, so that the amount of charge stored on the capacitor cannot determine the data, resulting in data damage. Therefore, the DRAM needs to be charged periodically. Due to the nature of this timed refresh, it is called “dynamic” memory.

Main control chip CPU/FPGA storage and single event flip science
Figure 9 Schematic diagram of DRAM structure

Static Random Access Memory (SRAM)

Static random access memory (Static Random Access Memory, SRAM) is formed on the basis of static flip-flops, and stores data by the self-preservation function of flip-flops.

The storage unit of SRAM is composed of six N-channel MOS tubes, of which four MOS tubes form basic RS flip-flops for memorizing binary codes; the other two are gated switches to control flip-flops and bit lines.

Main control chip CPU/FPGA storage and single event flip science
Figure 10 Schematic diagram of SRAM structure

The RS flip-flop is the most common basic digital latch unit, the main component of the LUT of the FPGA, with simple structure and flexible operation. The RS flip-flop has a fatal flaw and is prone to competition and risk.

Main control chip CPU/FPGA storage and single event flip science
Figure 11 Schematic diagram of digital logic of SRAM structure RS flip-flop

SRAM’s Single Event Upset Event (SEU)

RS flip-flops have very good latching performance, but they also have a design flaw. In practical applications, especially in some scenarios where there is radiation in the space environment, charged particles will appear to pass through the active region of the P-tube drain region. At this time, ionization generates a large number of electron-hole pairs on the particle track, forming a “transient current”.

Main control chip CPU/FPGA storage and single event flip science
Figure 12 Charging principle of single event flipping event

When an ionizing radiation occurs in the upper tube, through modeling, it can be roughly calculated that there is a certain relationship between the output voltage pulse, the accumulated charge, and the storage capacitor.

Main control chip CPU/FPGA storage and single event flip science

Suppose, if the input of the previous stage is logic 1, the output is logic 0, and the storage cell capacitance is 100fF, as long as the accumulated charge reaches 0.65pC-0.7pC, and the output voltage pulse amplitude is >0.7V, it is easy to judge that the output is high. flat. Before the voltage pulse at the output terminal returns to zero level, a logic 0 is written into the input through feedback, so that the voltage at the output terminal is fixed at a high level and becomes a logic 1, resulting in a particle flip effect. This is also the phenomenon of competition and adventure of digital circuits that we often say.

Main control chip CPU/FPGA storage and single event flip science
Figure 13 RS triggers cause the phenomenon of competitive risk taking

Single particle inversion effects and reinforcement

The single event flip will cause the rewriting of the stored data, especially most FPGA chips in the industry are mostly SRAM-based products. Once working in a harsh environment, it is very likely to cause the product to work abnormally and eventually lead to the failure of the entire system.

In general, it can be improved through circuit structure design reinforcement methods such as three-mode redundancy, time redundancy, and error detection and correction.

But the best solution is to use Flash FPGA. Since the storage principles of Flash-type FPGAs and SRAM FPGAs based on the principle of latches are completely different, it is difficult to rewrite logic cells by simple ionizing radiation, thereby improving reliability. At the same time, the power consumption of Flash technology products is much lower than that of SRAM.

At present, the FPGA based on Flash technology is mainly Microchip. It has an FPGA based on anti-fuse and Flash technology, and the mainstream product on the market is the third-generation SmartFusion® ProASIC®3/IGLOO®the fourth generation SmartFusion® 2/IGLOO2 and the 5th generation PolarFire/PolarFire SoC family.

Other memory (FRAM & EERAM)

Compared with traditional mainstream semiconductor memories, non-volatile read-only memory (ROM) and volatile random access memory (RAM), there are some faster, and non-volatile memories, such as ferroelectric memory (FRAM), and non-volatile random access memory (EERAM).

Ferroelectric Memory (FRAM)

As mentioned above, EEPROM stores data by operating the floating gate through a charge pump. The erasing and writing of the floating gate takes time, and the floating gate unit will also be destroyed, so there is a limit on the number of times. Ferroelectric memory (FRAM) is a non-volatile memory using a special process, using synthetic lead-zirconium-titanium (PZT) materials to form memory crystals.

When an electric field is applied to a ferroelectric crystal, the central atom moves in the crystal in the direction of the electric field. When an atom moves, it passes an energy barrier, causing charge breakdown. Internal circuitry senses charge breakdown and sets up the memory. When the electric field is removed, the central atom remains stationary and the state of the memory is preserved. The ferroelectric memory does not need to be updated regularly, and the data can continue to be saved after power failure, which is fast and not easy to be damaged.

Ferroelectric memory is a good thing, but has an Achilles heel, expensive. It is not cost-effective to use in low-cost industrial and consumer occasions.

Main control chip CPU/FPGA storage and single event flip science
Figure 14 Principle of ferroelectric memory

Nonvolatile Random Access Memory (EERAM)

In addition to the FRAM mentioned above, there is also a new type of non-volatile random access memory (EERAM), which is an exclusive recipe for Microchip.

Main control chip CPU/FPGA storage and single event flip science
Figure 15. Non-Volatile Random Access Memory Architecture

The working principle of EERAM is very simple. The inspiration comes from the SRAM powered by the backup battery. Its essence is that it does not require an external battery, but uses a small external capacitor. The IC monitors the common collector voltage between the SRAM and the EEPROM. Once the power supply voltage is low, the power is supplied through the capacitor, and the data of the SRAM is moved to the EEPROM to prevent signal loss.

For the stored data that needs to be updated continuously, EERAM adopts a special working method. When the abnormal supply voltage is monitored, Vcap is used as a backup power supply to transfer the data from SRAM to EEPROM, and automatically complete the safe transfer of data.

When the power supply returns to normal again, the data of the EEPROM is automatically exported to the SRAM. Moreover, you can also manually flash the data to the EEPROM.

Main control chip CPU/FPGA storage and single event flip science
Figure 16. Non-volatile random access memory uses capacitors to provide power for SRAM to transfer data

The advantages of EERAM include: automatic and reliable data retention through power failure, unlimited writes to data, low cost solution, and near-zero time interval writes. This device has high performance, and the price is not as expensive as ferroelectrics, which is very suitable for data loss prevention and cost-sensitive customers.

Main control chip CPU/FPGA storage and single event flip science
Figure 17 The working principle of non-volatile random access memory

Microchip’s package solution based on advanced storage technology

With the rapid outbreak of markets such as 5G communications, more and more customized products emerge one after another. Because most memories are exposed to very harsh environments, the market demand for universal chip FPGAs is increasing. Excepoint Shijian has a professional technical team. Microchip’s FLASH FPGA can effectively resist radiation to improve the reliability of the system. Solutions such as fast SuperFlash and innovative EERAM technology memory are also very distinctive and can help customers. Reduce storage costs and provide customers with more options for system design needs.

About Shijian——The Leading Authorized Distributor of components in Asia Pacific

Shijian is a complete solution provider, providing high-quality components, engineering design and supply chain for Asian electronics manufacturers including Original Equipment Manufacturers (OEMs), Original Design Manufacturers (ODMs) and Electronic Manufacturing Service Providers (EMS). Manage services. Shijian works closely with suppliers and electronics manufacturers to position new technologies and trends, and help customers incorporate these most advanced technologies into their products. The group has R&D centers in Singapore, China and Vietnam. Professional R&D teams continue to create new solutions to help customers improve cost-effectiveness and shorten time-to-market. The complete solutions and reference designs developed by Shijian can be applied in the fields of industry, wireless communication and consumer electronics. Shijian is a main board listed company in Singapore, headquartered in Singapore, with about 650 employees, and its business scope has expanded to more than 40 cities and regions in the Asia-Pacific region, covering Singapore, Malaysia, Thailand, Vietnam, China, India, Indonesia, the Philippines and Australia and more than ten countries. Shijian Group’s annual turnover in 2020 exceeded 1.1 billion US dollars. In 1993, Shijian established its regional headquarters in Hong Kong – Shijian Systems (Hong Kong) Co., Ltd., and officially began to develop its business in China. At present, Shijian has more than ten branches and offices in China, covering major large and medium-sized cities in China. With a professional R&D team, top field application support and rich market experience, Shijian enjoys a leading position in the Chinese industry.

Author: Yoyokuo