Important signal of FPGA: What is the function of clock?

The clock is the most important signal in FPGA design. Most of the device actions in the FPGA system are performed on the rising or falling edge of the clock. Whether it is between input, output or register and register, as long as the sampling is designed to the rising or falling edge of the clock, the setup time and hold time will be mentioned.

The clock is the most important signal in FPGA design. Most of the device actions in the FPGA system are performed on the rising or falling edge of the clock. Whether it is between input, output or register and register, as long as the sampling is designed to the rising or falling edge of the clock, the setup time and hold time will be mentioned.

The setup time (Tsu: set up TIme) refers to the time required for the data to change from unstable to stable before the clock edge arrives. If the setup time does not meet the requirements, the data will not be stably driven into the flip-flop on the rising edge of the clock. ; Hold time (Th: hold TIme) refers to the time that the data is held after it is stable. If the hold time does not meet the requirements, the data cannot be stably entered into the trigger either. The two indicators of setup time and hold time indicate that the device itself is not ideal (time delay, etc.). It is this undesirable characteristic that limits the operating frequency of the FPGA clock.

First of all, we all know that the setup TIme and holdup time are determined by the device, not that they can be changed as your FPGA design changes. So how is the FPGA clock frequency calculated? Without considering the clock delay jitter and other conditions, the delay of a signal from the D terminal to the Q terminal of the flip-flop is assumed to be Tcd. After coming out from the Q terminal, it will be delayed by the combination circuit. Note here that even if there is no combinational circuit, there is a delay just passing through the wire. This delay is called Tdelay. After this delay, the signal will go to the next flip-flop, and the set-up time tsetup of the flip-flop must be met, otherwise The clock cannot sample stable data. So the total of these three times should be smaller than the clock cycle, otherwise the data cannot enter the next flip-flop, then it will enter the metastable state.

As for the relationship between FPGA clock frequency and holdup time, Tcd+Tdelay+TsetupTholdup needs to be met during specific design, which means that Tholdup determines the lower limit of the shortest path, that is to say, the combinational logic cannot be too large or too small. This is where hold time works. In fact, the hold time can generally be satisfied, and the establishment time is generally satisfied as long as you consider it.

A simple schematic diagram of setup time and hold time is shown in Figure 1. In Figure 1, we see a dashed line before and after clk_r3. The first dashed line (the leftmost dashed line, the left represents the early appearance time, and the signals in the modelsim simulation sequence The period from left to right) to the rising edge of clk_r3 is the setup time, and the period from the rising edge of clk_r3 to the next dashed line (the rightmost dashed line) is the hold time. As mentioned earlier in the definition of the setup time and the hold time, there can be no data changes during this period, and the data must remain stable. And in this waveform, we really did not see any changes in the data of reg3in during the setup time and hold time, so we can stably latch the data of reg3in into the output reg3out of reg3.

Important signal of FPGA: What is the function of clock?

The waveform shown in Figure 2 below is the same signal, but we find that reg3in has changed during the setup time of clk_r3. The consequence is that the reg3in data latched by the rising edge of clk_r3 is uncertain, so the subsequent reg3out value Will also be in an uncertain state. For example, in the first clock cycle, originally reg3in should be at a stable low level, but due to the long delay time (Tcd+Tdelay) on the entire path, the data of reg3in has not stabilized during the establishment time of clk_r3. The signal level changes from high to low during the setup time, that is, an unstable state, then the result is that the final output of reg3out is not a certain state, it is likely to be a metastable state of fluctuating high and low, rather than The low level originally expected.

Important signal of FPGA: What is the function of clock?

The Links:   EVK75-050 TCG057QVLBA-G00

Author: Yoyokuo