Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

In recent years, the GPS global positioning system has played an important role in various fields such as urban transportation, navigation, meteorology, land surveying and mapping, and * modernization. Compared with the traditional RF front-end and signal processing part of GPS receivers which are realized by dedicated chips, the software receivers are based on hardware platforms such as FPGA and DSP, which quantize GPS signals into digital signals, and realize each of them through portable software algorithms. Kind of function.

introduction

In recent years, the GPS global positioning system has played an important role in various fields such as urban transportation, navigation, meteorology, land surveying and mapping, and * modernization. Compared with the traditional RF front-end and signal processing part of GPS receivers which are realized by dedicated chips, the software receivers are based on hardware platforms such as FPGA and DSP, which quantize GPS signals into digital signals, and realize each of them through portable software algorithms. Kind of function.

In the GPS software receiver, the high-frequency satellite signal is down-converted to an intermediate frequency signal through the radio frequency front end (RF), and then handed over to the DSP for baseband algorithm and navigation solution processing. The receiver has very high requirements for the continuity and real-time performance of signal reception and transmission. TI’s C67 series DSP has a wealth of peripherals, among which enhanced direct memory access (EDMA) and multi-channel buffered serial port (MCBSP) are important links that can complete the real-time transmission of GPS satellite data without the participation of the CPU.

1 Signal reception and transmission plan

This system uses TMS320C6713 DSP as the core processor of the system. The radio frequency front end chooses the GP2015 chip of ZARLINK Company to finish the signal correlation filtering, down-conversion and A/D sampling. Use a piece of FPGA chip EPlC3T144C8N between GP2015 and DSP to carry on relevant logic control, as shown in Fig. 1. The satellite signal power at the receiving end of the receiver antenna is about 2.7×10-6w, and the signal-to-noise ratio is low. It must first pass through a pre-filter module composed of an active antenna and a radio frequency filter, with a frequency of 1 575.42 The L1 band signal of MH2 is filtered to remove noise and other interference. The radio frequency front-end chip uses ZARLINK’s GP2015, a mainstream chip for GPS receivers. The chip itself uses a temperature-compensated crystal oscillator, and through a 1.4 GHz PLL loop, three local carrier signals are generated to achieve three-level frequency conversion for the high-frequency signal received by the antenna: 1 575. 42 MHz→175.42 MHz→35.42 MHz → 4. 309 MHz. Finally, the analog signal of 4. 309 MHz is converted with a sampling frequency of 5. 714 MHz to obtain two signals of SIGN and MAG, the center frequency of which falls on 1. 405 MHz. DSP uses MCBSP to receive 2 signals, and then obtains data from MCBSP’s receiving register through EI)MA, and transfers it to a designated external memory for CPU to call and process.

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

2 DSP hardware device settings

2.1 MCBSP settings

TMS320C6713 provides 2 MCBSP ports, which can realize full-duplex serial communication with industry standard encoder/decoder, AICS (analog interface chip) and other serial A/D and D/A interfaces. MCBSP provides double-buffered sending registers and triple-buffered receiving registers, allowing continuous data stream transmission.

MCBSP interfaces with peripherals through 7 pins (DX, DR, CLKX, CLKR, FSX, FSR, and CLKS). When receiving GPS signals, the data received on the DR pin first enters the receive transfer register (RSR), and then is copied to the receive buffer register (RBR), and then RBR copies the data to the data receive register (DRR), and waits EDMA controller reads. The GPS software receiver does not need to send data to the front end, so the sending function is not introduced. The operation of signal transmission is determined by the serial port control register SPCR and the pin control register PCR. The receiving control register RCR sets various parameters received, such as frame length.

When the signal is transmitted in the MCBSP, it is necessary to provide a synchronization clock and a frame synchronization signal, which can be generated by the internal sampling rate generator. It can also be driven by an external pulse source. In the scheme introduced in this article, the clock CLK of the SIGN and MAG signals of the RF front-end is provided by the FPGA. The LVDS interface of GP2015 generates differential signals, which is the same as ALT, which also has an LVDS interface. ERA’s FPGA chip EPlC3T144C8N interface, the FPGA passes the input 40 MHz differential signal by 7 frequency division, obtains 5.714 MHz clock and provides it to GP2015 and DSP as the intermediate frequency sampling clock signal and the external clock signal of MCBSP respectively . At the same time, the 5.714 MHz signal is divided by 32, and the McBSP0 and MCBSP1 provided to the DSP processor are used as frame synchronization signals. The schematic diagram of the system interface and the timing diagram of related signals are shown in Figure 2 and Figure 3.

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

2.2 EDMA settings

The EDMA controller of TMS320C6713 provides 16 enhanced channels, each of which is independent of each other. Without the participation of the CPU, the EDMA controller can complete the data movement between the on-chip memory and the peripherals in the background. It consists of the following parts: event and interrupt processing register, event encoder, parameter RAM, address hardware generator. The event register completes the capture control of the EDMA event, the event generates a synchronization signal to trigger the EDMA channel to start data transmission; the EDMA parameter RAM stores the transmission parameters related to the event; the address hardware generator generates the read/write operation between the EMIF and the peripheral The required address signal. The 16 channels of EDMA share an interrupt signal EDMA_INT. When EDMA completes one transmission task, it can trigger an EDMA interrupt. The parameter RAM of EDMA of TMS320C6713 includes 6 words, its structure is shown as in Fig. 4. In OPT, users can set the event priority, data unit size, source address/destination address change mode, transmission end code, whether to enable the link (1inking) function, and synchronous transmission by setting each position “0” or “1” Way etc.

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

3 Ping-pong buffer real-time transmission

3.1 Transmission analysis

The GPS software receiver receives the signal through the MCBSP port, saves the satellite data in the designated mapped memory, and then the EDMA channel transfers the data to the on-chip L2 cache for the CPU to extract and process. The L2 cache has half the clock speed of the CPU, and the CPU processing data is faster. CPU data processing must be synchronized with EDMA data transmission, that is, to ensure that EDMA transmits data to the buffer before CPU access. However, limited by the capacity of the on-chip secondary memory and the real-time nature of the data, it will face a problem: the data written in the buffer later may overwrite the data written in the earlier but not yet processed. To this end, it is necessary to open up two pairs of ping-pong buffers in the L2 cache to receive GPS SIGN and MAG signals respectively, and use the multi-group parameter link function of EDMA, according to the characteristics of real-time data transmission, to perform the EDMA parameter RAM set up.

Take receiving the SIGN signal as an example, first open up an EDMA channel 1, and its trigger event is set as the transmission of MCBSP0. The entry parameter 0PT is set to one-dimensional single frame transmission, using read/write synchronization mode, the data unit length is 32 bits, the source address is fixed, the destination address is incremented by the length of 1 data unit, and the link function is enabled. SRC is set to the mapping address of DRR2 in MCBSP: DST is set to the first address of ping-buffer, ELECNT is set to the size of the buffer, FRMCNT, FRMIDX, ELEIDX, and ELERLD are all set to 0. Then open up 2 free EDMA channels-Channel 2 and Channel 3, its settings are the same as before, except that the DST destination address points to pong-buffer and ping-buffer respectively. Then the link address link of EDMA channel 1 points to channel 2, the link address of channel 2 points to channel 3, and the link address of channel 3 points to channel 2. The EDMA link function of the MAG signal and the coordination setting of the ping-pong buffer are the same, and will not be described again. The relevant settings of the ping-pong buffer are shown in Figure 5.

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

3.2 Program settings

The program that uses EDMA and MCBSP to transmit GPS signals in real time was written and debugged in the CCS3.3 environment, and the results proved that the data transmission was correct. The following procedure briefly describes the software transmission configuration of the GPS software receiver.

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

Design of Real-time GPS Satellite Data Transmission System Based on TMS320C6713 DSP and GP2015 Chips

Concluding remarks

Based on GP2015 and TMS320C6713, this paper proposes a general scheme of a software receiver, and uses MCBSP and EDMA to realize the real-time reception and transmission of GPS satellite signals. The article focuses on the relevant parameter settings of DSP hardware devices, as well as the use of ping-pong cache, and gives some programs for reference.

The Links:   SKM200GB123D LM64C081

Author: Yoyokuo