“Infineon is the first to discover the drift of VGS(th) under long-term stress due to dynamic operation and proposes a region of operating gate voltage designed to minimize drift over lifetime.[1].

“

**About the Author**

Dr. André Lenze and Paul Salmen,

Infineon Technologies AG (Wallstein, Germany)

**introduction**

Threshold voltage shift (VGS(th)) under practical application conditions has been the focus of SiC over the past few years.

Infineon is the first to discover the drift of VGS(th) under long-term stress due to dynamic operation and proposes a region of operating gate voltage designed to minimize drift over lifetime.[1].

After continuous research and continuous optimization, the new CoolSiC™ MOSFET M1H now has a significant improvement in VGS(th) stability with negligible drift effects in almost all cases.

**Symptom**

VGS(th) drift phenomena are often described by high temperature gate bias stress testing (DC-HTGS), which is performed following test guidelines defined by standards such as JEDEC.

Recent results show that compared with the corresponding static gate stress test (DC-HTGS), including V_(GS(off))

Figure 1: Drift during continuous gate switching stress:

VGS,(on)=20V;VGS(off)=−10V;

Tvj,max=150°C and f=500kHz.[1]

Our conclusion is that under stress conditions with more than 10⁸ switching cycles, AC drift is the main cause of stress; when the number of switching cycles is small, DC drift is the main cause of stress.

The data show that switching stress causes a slow increase in VGS(th) over time. As the threshold voltage VGS(th) increases, an increase in channel resistance (Rch) can be observed.This phenomenon is described by equation (1), where L is the channel length, W is the channel width, μn is the electron mobility, Cox is the gate oxide capacitance, and VGS(on) is the on-state gate voltage, VGS(th) is the threshold voltage of the device[1].

The total RDS(on) is determined by the sum of the individual resistances, namely the channel resistance (Rch), the junction field effect transistor resistance (RJFET), the epitaxial layer resistance of the drift region (Repi) and the resistance of the highly doped SiC substrate (RSub). Equation (2) describes the overall composition of the total RDS(on).

Therefore, an increase in VGS(th) results in a slight increase in channel resistance, resulting in an increase in RDS(on) and conduction losses over time.

**gate switching stress**

To ensure and predict the long-term stability of the electrical parameters of our CoolSiC™ MOSFETs during typical switching operation, we have developed and adopted a new stress test: the Gate Switch Stress Test (GSS). This test allows you to directly determine electrical parameter drifts that typically operate in positive and negative drive voltage modes (positive V(GS,on): on; negative VGS(OFF): off). This test allows developers to quantify the new failure mechanisms described above and, therefore, is necessary for the qualification of SiC MOSFETs.

GSS testing covers all important drift phenomena, including those that occur during normal device operation. Except for the missing load current (which by itself does not change the drift behavior we observe)[3]we simulate the application as closely as possible by keeping the gate switching characteristics (e.g., voltage slope) similar to typical application conditions (see Figure 2)[1]. To cover the potential effects of gate signal overshoot and undershoot, which are very common in practical SiC MOSFET applications, we stress them at the maximum gate voltage and maximum static junction temperature (Tvj,op) allowed by the datasheet. implement the worst case.

Figure 2: When the frequency f=500kHz,

Typical GSS gate-source stress signal.[1]

Worst-case testing gives customers confidence that they can use the device over the full specification range without exceeding the drift limit. Therefore, this method guarantees excellent reliability of the device and also facilitates the calculation of safety margins.

In addition to VGS(th), other parameters such as gate leakage current IGSS are also measured and are consistent across the hardware under test[1].

**Worst-case end-of-life drift assessmentand its impact on applications**

In the process of developing inverters, a major task is to predict the service life of the equipment. Therefore, reliable models and information must be provided. After extensive testing under various operating conditions, we were able to develop a predictive semi-empirical model that describes the threshold voltage as a function of task curve parameters such as: stress time (tS), gate Pole Bias Low (VGS(off)), Gate Bias High (VGS(on)), Switching Frequency (fsw) and Operating Temperature (T) (ΔVGS(th) (tS,VGS(off) ,VGS(on),fsw,T))[3].

Based on this model, we established a method to estimate the threshold voltage drift, using the worst-case end-of-life curve (EoAP) to calculate the relative R(DS(on)) drift. In an application, running at an arbitrary frequency for a certain amount of time, we can calculate the total number of switching cycles (NCycle) until EoAP. Then, the relative RDS(on) drift was read out using NCycle.

The number of cycles depends on the switching frequency and operating time. Typical hard-switched industrial applications (eg, solar string inverters) use switching frequencies of 16-50 kHz. The switching speeds of inverters using resonant topologies typically exceed 100kHz. The target life for these applications is usually 10-20 years, while the actual operating time is usually 50%-100%.

**The following example provides a sample evaluation:**

• Target life[年]: 20

• Actual working hours[%]: 50%=>10 years

• Actual working hours[s]: 315,360,000s (10 years)

• On-off level[kHz]: 48

• Cycle duration[s]: 1/switching frequency=0.0000208

• Cycles at end of life = ~1.52E+13

With an on-voltage of 18V, the relative change in RDS(on) is expected to be less than 6% at 25°C and less than 3% at 175°C, see Figure 3 (green dots in Figure 3).

Figure 3: VGS(on)=18V, Tvj, op=25°C, 125°C and 175°C [2]Relative RDS(on) change when

Figure 4 example based on the recently introduced EasyPACK™ FS55MR12W1M1H_B11 (three-phase inverter bridge configuration in a DC-AC inverter) illustrating the impact of changes in the RDS(on) prediction[4]. This example is an application where conduction loss (Pcon) accounts for a large proportion of the loss distribution. Tvj,op rises by only 2K from the initial worst-case EoAP of 148°C to 150°C. It turns out that even after 20 years of use, slight changes in RDS(on) lead to negligible increases in Tvj,op.

Figure 4. Worst-case EoL evaluation: Vdc: 800V, Irms: 18A, fout: 50Hz, fsw: 50kHz, cos(φ): 1, Th=80°C.

Text in the picture:

Power loss: power loss

Initial point: initial point

Worst-case EoAP: Worst-case EoAP

This approach means that the maximum drift should occur in the worst case described. With the new M1H chip, customers will be able to select the parameters best suited for their application from the range of specifications in the datasheet. Parasitic overshoot and undershoot in the gate signal do not affect drift and need not be considered from an application perspective. Therefore, time and effort can be saved.

Note: For applications operating at well-controlled gate bias levels, well below the datasheet maximum limits, e.g. +18V/-3V, the magnitude of the change in RDS(on) for the same number of switching cycles even smaller.

**in conclusion**

We investigated the threshold voltage characteristics under practical application conditions by conducting long-term tests under various switching conditions. We have developed and employed a stress testing procedure to determine the worst-case EoAP parameter drift under realistic application switching conditions, providing our customers with a reliable predictive model.

Among other key improvements, the recently introduced 1200V CoolSiC™ MOSFET, the M1H, has shown excellent stability and reduced effects of drift phenomena.

references

[1] Infineon Application Note 2018-09

[2] P. Salmen, MW Feil, K. Waschneck, H. Reisinger, G. Rescher, T. Aichinger: A new test procedure for practical evaluation of end-of-life electrical parameter stability of SiC MOSFETs in switching operation; 2021 IEEE International Reliability Physics Symposium (IRPS) (2021)

[3] Infineon: White Paper 08-2020: How Infineon Controls and Ensures the Reliability of SiC-Based Power Semiconductors, page 11C21;

[4] Data Sheet FS55MR12W1M1H_B11