# Comprehensive analysis of switching regulator noise, ADI teaches you how to easily reduce noise

In general, the output voltage of conventional switching regulators is considered to be quite noisy compared to the output of a low dropout (LDO) regulator. However, the LDO voltage can cause significant additional thermal problems and complicate the power supply design. A thorough understanding of switching regulator noise is necessary to help design low-noise switching solutions that produce low-noise performance comparable to LDO regulators. The target of the analysis and evaluation in this article is a buck regulator with current mode control, as it is most commonly used in applications.Signal analysis is the key to understanding switching ripple noise, current broadband noise characteristics (and their sources), high frequency spike noise due to switching

In general, the output voltage of a traditional switching regulator is considered to be quite noisy compared to the output of a low dropout (LDO) regulator. However, the LDO voltage can cause significant additional thermal problems and complicate the power supply design. A thorough understanding of switching regulator noise is necessary to help design low-noise switching solutions that produce low-noise performance comparable to LDO regulators. The target of the analysis and evaluation in this article is a buck regulator with current mode control, as it is most commonly used in applications. Signal analysis is the primary method for understanding switching ripple noise, current broadband noise characteristics (and their sources), and switching-induced high-frequency spikes. This article will discuss switching regulator PSRR (Power Supply Rejection Ratio, which is important for input noise rejection) and signal analysis methods.

Switching Ripple Noise

This section introduces the formula for calculating the output ripple of a buck converter based on fundamental and harmonic theory. Ripple is always the dominant noise in a switching regulator because the peak-to-peak voltage amplitude is typically a few mV to tens of mV, depending on the switching regulator topology and basic operation. It should be seen as a periodic and predictable signal. If operating at a fixed switching frequency, it can be easily identified and measured by an oscilloscope in the time domain, or by Fourier decomposition in the frequency domain.

Figure 1 shows a typical buck regulator. The two switches are turned on and off alternately, so the SW node voltage VSW is an ideal square wave, which in turn is transferred to the duty cycle and input voltage. VSWVSW can be expressed by the following formula:

in:

VIN is the input voltage. D is the duty cycle; for buck regulators, it is equal to VOUT/VIN

After VIN is determined, The VSW fundamental and harmonic components depend only on the duty cycle. Figure 2 shows the VSW fundamental and harmonic amplitudes in relation to the duty cycle. When the duty cycle is close to half, the ripple amplitude is dominated by the fundamental wave.

The buck regulator output LC stage transfer function is as follows:

Among them, L is the output inductance value, DCR is the inductance resistance value, and CL is the inductance parallel capacitance value.

COUT is the output capacity value. ESL is the capacitor series inductance value. ESR is the capacitor series resistance value.

Therefore, VOUT can be expressed as follows:

To simplify the calculations, we assume that the output LC stage is 20 dB/decade, followed by the VOUT ripple fundamental and harmonic amplitudes related to the duty cycle, as shown in Figure 3. When the duty cycle is close to half, the third or odd harmonics will be higher than the even harmonics. Due to LC suppression, higher harmonics will have lower amplitudes and a very small proportion compared to the total ripple amplitude. Likewise, the fundamental amplitude is the dominant component in the switching regulator output ripple.

For a buck regulator, the fundamental amplitude is related to the input voltage, duty cycle, switching frequency, and LC stage; however, all of these parameters affect application requirements such as efficiency and solution size. To further reduce the ripple, it is recommended to add a post filter.

Broadband noise in switching regulators is random amplitude noise on the output voltage. It can be expressed in terms of the noise density over the entire frequency range, in V/√Hz z, or in Vrms, which is inseparable from the density over the frequency range. Due to the limitations of silicon process and reference filter design, broadband noise is mainly located in the 10Hz to 1MHz frequency range of switching regulators, and it is difficult to reduce it by adding filters in the low frequency range.

Typical buck regulator broadband noise peak-to-peak amplitude voltage is about 100μV to 1000μV, which is much lower than switching ripple noise. If additional filters are used to reduce switching ripple noise, broadband noise can become the dominant noise in the output voltage of the switching regulator. Figure 4 shows that when there is no additional filter, the main source of output noise for a buck regulator is switching ripple. Figure 5 shows that when additional filters are used, the main source of output noise is broadband noise.

In order to identify and analyze switching regulator output broadband noise, regulator control scheme and module noise information must be obtained. For example, Figure 6 shows a typical current-mode buck regulator control scheme and block noise source injection.

For the obtained control loop transfer function and block noise characteristic information, there are two different kinds of noise: loop input noise and in-loop noise. Loop input noise within the control loop bandwidth is transmitted to the output, while noise outside the loop bandwidth is attenuated. For switching regulators, designing low-noise EAs and references is critical because unity feedback gain keeps the noise level constant rather than increasing it as the output voltage level increases. The biggest challenge is finding the largest source of noise in the entire system and reducing that noise in the circuit design. Optimized for low-noise technology, the ADP5014 uses a current-mode control scheme and a simple LC external filter to achieve sub-20µVrms noise performance over the 10Hz to 1MHz frequency range. The output noise performance of the ADP5014 is shown in Figure 7.

High frequency spikes and ringing

The third type of noise is high frequency spikes and ringing noise because the output voltage is generated by the switching regulator turn-on or turn-off transients. Consider parasitic inductance and capacitance in silicon circuits and PCB traces; for buck regulators, fast current transients will cause high frequency voltage spikes and ringing at the SW node. Spike and ringing noise increases with current load. Figure 8 shows how a buck regulator forms a spike. Depending on the on/off slew rate of the switching regulator, the highest peaking and ringing frequencies will be in the 20MHz to 300MHz range, and the output LC filter may not be very effective in rejection due to parasitic inductance and capacitance. Compared to all the above discussion about conduction paths, the worst is the radiated noise from the SW and VIN nodes, the output voltage and other analog circuits suffer due to its very high frequency.

To reduce high frequency spikes and ringing noise, effective methods are recommended for application and chip design implementation. First, an additional LC filter or bead should be used on the termination load. Typically, this makes the spike noise on the output much smaller than the ripple noise, but adds higher frequency components. Second, noise sources at the SW and input nodes should be shielded or kept away from the output side and sensitive analog circuits, and the output Inductor should be shielded. Careful placement and routing are important to the design. Third, optimize the on/off slew rate of the switching regulator and minimize the parasitic inductance and resistance of the switching regulator, thereby effectively reducing the SW node noise. ADISilentSwitchr® technology also helps reduce VIN node noise through chip design.

Switching Regulator PSRR

PSRR reflects the ability of a switching regulator to suppress the transmission of input power supply noise to the output. This section analyzes the PSRR performance of the buck regulator in the low frequency range. High frequency noise affects the output voltage primarily through the radiated path rather than the conduction path discussed earlier.

According to the buck small signal diagram shown in Figure 9, the buck PSRR can be expressed as follows:

in:

Compare the signal mode calculations with the simulation results. The small signal mode is valid and is consistent with the simulation results.

The PSRR performance of a T switching regulator depends on the loop gain performance in the low frequency range. The switching regulator’s inherent LC filter suppresses input noise in the IF range (100Hz to 10MHz). The rejection performance in this range is much better than the LDO PSRR. Therefore, switching regulators have ideal PSRR performance due to their high loop gain at low frequencies, while the inherent LC filter affects the mid-frequency range.

in conclusion

More and more analog circuits, such as ADC/DAC, clocks, and PLLs, require clean, high-current power supplies. Each device has different requirements and specifications for power supply noise in different frequency ranges. A thorough understanding of the different types of switching regulator noise and awareness of power supply noise requirements is necessary to design and implement high efficiency, low noise switching regulators that meet the low noise specifications of most analog circuit power supplies. Compared with LDO regulators, this low noise switching solution will have higher power efficiency, smaller solution size and lower cost.

Author: Yoyokuo